Apparatus, method and memory device for error correction by increasing or decreasing a read voltage and analyzing frequency information for a read error pattern

ABSTRACT

An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2008-0048264, filed on May 23, 2008, in the KoreanIntellectual Property Office (KIPO), the entire contents of which areincorporated herein by reference.

BACKGROUND

1. Field

Example embodiments relate to methods that may correct read errors ofdata of memory devices. Also, example embodiments relate to apparatusesand/or methods that may correct errors of read data of multi-level cell(MLC) memory devices or multi-bit cell (MBC) memory devices.

2. Description of Related Art

Recently, a multi-level cell (MLC) memory device that may store data oftwo or more bits in a single memory cell has been proposed in responseto a need for higher integration of memory. The MLC memory device mayalso be referred to as a multi-bit cell (MBC) memory. However, as thenumber of bits programmed in the single memory cell increases,reliability may deteriorate and a read-failure rate may increase. Toprogram ‘m’ bits in the single memory cell, any one of 2^(m) thresholdvoltages may need to be generated in the memory cell. Threshold voltagesof memory cells where the same data is programmed may generate adistribution within a predetermined range due to the minute electricalcharacteristic difference between the memory cells. Each thresholdvoltage distribution may correspond to one of 2^(m) data valuesgenerated by ‘m’ bits.

However, since a voltage window for a memory device may be limited, adistance between 2^(m) distributions of threshold voltages betweenadjacent bits may decrease as ‘m’ increases, and the distributions maybe overlapped as the distance between the distributions decreases. Whenthe distributions are overlapped, the read-failure rate may increase.

As the MLC memory device has been widely and recently used, errorcontrol codes or error control coding or error correction codes (ECC)that may detect an error occurring when storing and reading the data andcorrect the detected error have been actively used.

When the data is maintained for a long time, due to a lateral movementof a charge which may be caused by an electrostatic attractive forcebetween the charge stored in the memory cell and the charge stored in anadjacent cell, a charge trap memory including a multi-level cell mayneed to efficiently correct a read error.

SUMMARY

Example embodiments may provide apparatuses and/or methods that mayselect a codeword corresponding to a read word based on a selected readerror pattern when the read word being read and extracted from amulti-level cell (MLC) is outside an error correcting capability range.

Example embodiments may also provide apparatuses and/or methods that maymanage, in parallel, error correction codes (ECC) and a read errorpattern having a high probability that a read error occurs, therebyeffectively correcting the read error that may occur due to a lateralcharge movement between adjacent cells.

According to example embodiments, an error correction apparatus mayinclude: a determination unit configured to determine whether a numberof words in a read word being read and extracted from an MLC exists inan error correcting capability range; a read voltage control unitconfigured to either increase or decrease a read voltage applied to theMLC when the number of errors in the read word is outside the errorcorrecting capability range; and a codeword determination unitconfigured to analyze a bit error based on the increase or decrease ofthe read voltage, and to select a codeword corresponding to the analyzedbit error based on a selected read error pattern.

According to example embodiments, a memory device may include: an MLCarray including a plurality of MLCs; an error correction unit configuredto analyze a bit error when a read word being read and extracted from anMLC is outside an error correcting capability range to select and decodea codeword with respect to the read word based on a selected read errorpattern; and a host interface configured to transmit the decodedcodeword to a host.

According to example embodiments, an error correction method mayinclude: determining whether a number of errors in read word being readand extracted from an MLC exists in an error correcting capabilityrange; either increasing or decreasing a read voltage applied to the MLCwhen the number of errors in the read word is outside the errorcorrecting capability range; and analyzing a bit error based on theincrease or decrease of the read voltage, and selecting a codewordcorresponding to the analyzed bit error based on a selected read errorpattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of example embodiments willbecome more apparent by describing in detail example embodiments withreference to the attached drawings. The accompanying drawings areintended to depict example embodiments and should not be interpreted tolimit the intended scope of the claims. The accompanying drawings arenot to be considered as drawn to scale unless explicitly noted.

FIG. 1 is a block diagram illustrating a memory device according toexample embodiments;

FIG. 2 is a block diagram illustrating a configuration of an errorcorrection unit of FIG. 1;

FIG. 3 illustrates an operation of the error correction unit of FIG. 1;

FIG. 4 is a flowchart illustrating a method of correcting a read erroraccording to example embodiments;

FIG. 5A is a flowchart illustrating a method of selecting a codewordbased on a read error pattern to correct an error according to exampleembodiments;

FIG. 5B is a flowchart illustrating another method of selecting acodeword based on a read error pattern to correct an error according toexample embodiments; and

FIG. 5C is a flowchart illustrating still another method of selecting acodeword based on a read error pattern to correct an error according toexample embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Detailed example embodiments are disclosed herein. However, specificstructural and functional details disclosed herein are merelyrepresentative for purposes of describing example embodiments. Exampleembodiments may, however, may be embodied in many alternate forms andshould not be construed as being limited to only the embodiments setforth herein.

Accordingly, while example embodiments are capable of variousmodifications and alternate forms, embodiments thereof are shown by wayof example in the drawings and will herein be described in detail. Itshould be understood, however, that there is not intent to limit exampleembodiments to the particular forms disclosed, but to the contrary,example embodiments are to cover all modifications, equivalents, andalternatives falling within the scope of example embodiments. Likenumbers refer to like elements throughout the description of thefigures.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it may be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between”, “adjacent” versus “directlyadjacent”, etc.).

It will be understood that although the terms first, second, third,etc., may be used herein to describe various elements, components,regions, layers, and/or sections, these elements, components, regions,layers, and/or sections should not be limited by these terms. Theseterms are only used to distinguish one element, component, region,layer, and/or section from another element, component, region, layer,and/or section. For example, a first element, component, region, layer,and/or section could be termed a second element, component, region,layer, and/or section without departing from the teachings of exampleembodiments.

Spatially relative terms, for example “beneath,” “below,” “lower,”“above,” “upper,” and the like may be used herein for ease ofdescription to describe the relationship of one component and/or featureto another component and/or feature, or other component(s) and/orfeature(s), as illustrated in the drawings. It will be understood thatthe spatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting. As usedherein, the singular forms “a,” “an,” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes,” and/or “including,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, and/or components.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belongs. Itwill be further understood that terms, for example those defined incommonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand should not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

Example embodiments having thus been described, it will be obvious thatthe same may be varied in many ways. Such variations are not to beregarded as a departure from the intended spirit and scope of exampleembodiments, and all such modifications as would be obvious to oneskilled in the art are intended to be included within the scope of thefollowing claims.

Reference will now be made to example embodiments, which are illustratedin the accompanying drawings, wherein like reference numerals may referto like components throughout.

Hereinafter, an error correction apparatus, a method thereof, and amemory device including the apparatus according to example embodimentsare described in detail with reference to the attached drawings. Whendetailed descriptions related to a well-known related function orconfiguration are determined to make the spirits of example embodimentsambiguous, the detailed descriptions will be omitted herein. Also, termsused throughout the present specification are used to appropriatelydescribe example embodiments, and thus may be different depending upon auser and an operator's intention, or practices of application fields ofexample embodiments. Therefore, the terms must be defined based ondescriptions made through example embodiments.

FIG. 1 is a block diagram illustrating a memory device 100 according toexample embodiments.

Referring to FIG. 1, the memory device 100 may include a multi-levelcell (MLC) array 110, an error correction unit 120, and a host interface130.

The MLC array 110 may include a plurality of MLCs. A process of storingdata in an MLC of a non-volatile memory including a flash memory, anElectrically Erasable Programmable Read Only Memory (EEPROM), and thelike may be referred to as a programming process, and may correspond toa process of changing a threshold voltage of the MLC.

A process of programming the data in the MLC of the non-volatile memorymay be performed by a mechanism including Fowler-Nordheim tunneling (F-Ntunneling), a hot carrier effect, and the like. F-N tunneling may changethe threshold voltage of the MLC. A single-bit cell may have a lowthreshold voltage level or a high threshold voltage level, and mayexpress data of “0” or “1” using two threshold voltage levels.

In a Charge Trap Flash (CTF) memory device, the MLC array 110 mayinclude an insulation layer including a charge trap site that may trap acharge.

A charge potential difference between adjacent cells may exist in theMLC. A lateral electric field may occur due to the potential difference,and the charge stored in a charge trap layer of the MLC may move in aword line direction.

When the charge stored in the charge trap layer moves in the word linedirection, a threshold voltage of a programmed cell may graduallydecrease, and the stored data may be lost, thereby deterioratingreliability of a memory.

In the charge trap layer, for example silicon nitride (Si₃N₄), mobilityof the charge may change so that the charge moves non-linearly based ona strength of an electric field that may be applied to the charge traplayer, and as the strength of the electric field increases, chargemobility may increase non-linearly.

In a four-level MLC, a cell may have three levels of state 00, state 01,or state 10 as a programming state, and may have state 11 as a deletionstate. Since the programming state may be classified into three states,a maximum of threshold voltages of the programming state may have isabout 4.5 V, and may include a state from −2 V to −4 V as the deletionstate. When the data is saved for a long time, a movement of mostelectrons stored in the cell to the adjacent cell may occur.Accordingly, the data may not maintain an initial input state.

Error correction codes (ECC) may be used for correcting an error thatoccurs when the data is read. A process of adding the ECC to initialdata prior to storing the data in the MLC may be referred to as ECCencoding, and a process of separating added information and the initialinformation from the data being read and extracted from the MLC torestore the initial information may be referred to as ECC decoding.

Depending on ECC decoders, when a number of errors of an input codewordis less than or equal to the error correcting capability of an ECC code,all errors of the input codeword may be corrected. Block codes and thelike may be examples of codes whose error correcting capability isexplicitly shown. As examples of the block codes, there are Bose,Ray-Chaudhuri, Hocquenghem (BCH) codes, Reed-Solomon (RS) codes, and thelike, and as examples of decoding schemes for the block codes, there area Meggitt decoding scheme, a Berlekamp-Massey decoding scheme, and aEuclid decoding scheme, and the like.

However, when the number of errors of the input codeword is beyond theerror correcting capability of an ECC code, the accurate and actualcodeword may not be selected by a general ECC decoding scheme.

For this, the error correction unit 120 according to example embodimentsmay analyze a bit error when the number of errors in a read word beingread and extracted from the MLC array 110 is outside an error correctingcapability range to select and decode the codeword with respect to theread word based on a selected read error pattern.

The host interface 130 may transmit the decoded codeword to a host 200.The host 200 may include a controller of a mobile device, a controllerof a computer apparatus, and the like. The host interface 130 mayperform a control and buffering function for an interface between thehost 200 and the MLC array 110.

The read error pattern may include a data error pattern that occurscorresponding to a data storage pattern between adjacent cells stored inthe MLC.

The read error pattern may include the data error pattern that occursdue to a lateral electric field between the adjacent cells of the MLCarray 110, and the data error pattern may correspond to a thresholdvoltage change of the MLC array 110 due to a lateral charge movementcaused by the lateral electric field.

Hereinafter, referring to FIG. 2, the error correction unit 120 of FIG.1 is described in detail.

FIG. 2 is a block diagram illustrating a configuration of the errorcorrection unit 120 of FIG. 1.

Referring to FIG. 2, the error correction unit 120 may include adetermination unit 121, a read voltage control unit 122, and a codeworddetermination unit 123.

The determination unit 121 may determine whether the number of errors ina read word being read and extracted from an MLC array 110 exists in anerror correcting capability range.

The read voltage control unit 122 may either increase or decrease a readvoltage applied to the MLC array 110 when the number of errors in a readword is outside the error correcting capability range. The read voltagecontrol unit 122 may complete reading data at an initial read voltage,for example, V=1.0V, and may gradually increase or decrease the readvoltage by ΔV, for example, 0.1˜05.V, while reading data.

The codeword determination unit 123 may analyze the bit error based onthe increase or decrease of the read voltage, and select the codewordwith respect to the read word based on a selected read error pattern,the codeword corresponding to the analyzed bit error.

When a number of bit errors with respect to the analyzed bit error doesnot increase or decrease, the codeword determination unit 123 may selectthe codeword based on the read error pattern.

According to example embodiments, the codeword determination unit 123may analyze frequency information about the read error pattern, and mayselect a codeword having a level of association with the read errorpattern which is above a reference value or the maximum level ofassociation. For example, the MLC array 110 may store data relating tothe frequency with which different read error patterns occur for eachcodeword. With reference to a particular read error pattern, codeworddetermination unit 123 may choose a codeword for which the particularread error pattern has occurred more than a reference number of times,or codeword determination unit may choose a codeword for which theparticular read error pattern has occurred a maximum number of timeswhen compared to other codewords.

According to example embodiments, the codeword determination unit 123may analyze a Hamming distance between the read word and each of a setof candidate codewords, and may select the codeword in which theanalyzed Hamming distance is below a reference value or the minimum.

According to example embodiments, the MLC array 110 may store errorpattern information about a weight of the read error pattern includingdata before encoding, and the codeword determination unit 123 may selectthe codeword based on at least one of the error pattern information andthe analyzed Hamming distance.

The read error pattern according to example embodiments may include adata error pattern that occurs corresponding to a data storage patternwith respect to the data stored between adjacent cells of the MLC array110.

According to example embodiments, the read error pattern may include thedata error pattern that occurs due to a lateral electric field betweenthe adjacent cells of the MLC array 110. The data error pattern maycorrespond to a threshold voltage change of the MLC array 110 due to alateral charge movement caused by the lateral electric field, and thecodeword determination unit 123 may select the codeword including thedata error pattern.

The error correction unit 120 according to example embodiments mayfurther include a decoding unit 124 configured to decode the selectedcodeword.

Hereinafter, referring to FIG. 3, an operation of the error correctionunit 120 of FIG. 1 is described in detail.

FIG. 3 illustrates the operation of the error correction unit 120 ofFIG. 1.

Referring to FIG. 3, a relation between a threshold voltage and 2-bitdata stored by MLCs is illustrated.

Threshold voltage distributions of the MLCs are shown as a number of theMLCs corresponding to each of the threshold voltages.

Since minute electrical differences between each of the MLCs exist, thethreshold voltages of the MLCs may generate distributions withpredetermined ranges.

A distribution 311 may denote the MLCs storing data “11”.

A distribution 312 may denote the MLCs storing data “10”.

A distribution 313 may denote the MLCs storing data “00”.

A distribution 314 may denote the MLCs storing data “01”.

The memory device 100 may decide a Most Significant Bit (MSB) stored inMLCs of a memory page using a second read voltage level 322. The memorydevice 100 may decide, as “0”, the MSB stored in the MLCs having thethreshold voltage higher than the second read voltage level 322, and maydecide, as “1”, the MSB stored in the MLCs having the threshold voltagelower than the second read voltage level 322.

The memory device 100 may decide a Least Significant Bit (LSB) stored inthe MLCs of the memory page using a first read voltage level 321 and athird read voltage level 323. The memory device 100 may decide, as “1”,the LSB stored in the MLCs having the threshold voltage lower than thefirst read voltage level 321. The memory device 100 may decide, as “1”,the LSB stored in the MLCs having the threshold voltage higher than thethird read voltage level 323. The memory device 100 may decide, as “0”,the LSB stored in the MLCs having the threshold voltage being higherthan the first read voltage level 321 and being lower than the thirdread voltage level 323.

A state 315 may denote that the threshold voltage of the identified MLCis included in the distribution 314 when programming data. The dataprogrammed in the identified MLC may correspond to “01”.

In a CTF memory device according to example embodiments, a charge storedin the MLC array 110 move laterally due to a lateral electric fieldbetween adjacent cells and may decrease or increase the thresholdvoltage. When having a data storage pattern of storing data of a highestlevel in a cell, for example, a state where the threshold voltage has ahighest value, and storing data of a lowest level in an adjacent cellthereof, for example, a state where the threshold voltage has a lowestvalue, a lateral potential difference between the adjacent cells maybecome maximum, and a lateral charge movement may occur most actively.

In FIG. 3, when the data storage pattern between the adjacent cells ofthe MLC array 110 includes state “11” where the threshold voltagecorresponds to a lowest level and state “01” where the threshold voltagecorresponds to a highest level (‘110111’ or ‘011101’), the lateralcharge movement may occur most easily.

An arrow 340 may denote a change of the threshold voltage of theidentified MLC caused by the lateral charge movement occurring due tothe lateral electric field.

A state 335 may denote that the threshold voltage of the identified MLCis included in a distribution 333 when the data is read and extracted.The data read from the identified MLC may correspond to “00”.

The read voltage control unit 122 may either increase or decrease a readvoltage applied to the MLC when the number of errors in the read wordbeing read and extracted from the MLC is outside the error correctingcapability range.

The codeword determination unit 123 may analyze the bit error based onthe increase or decrease of the read voltage, and select the codewordwith respect to the read word, the codeword corresponding to theanalyzed bit error based on the read error pattern where an errorincluding the above-described data storage pattern easily occurs.

As described above, the read error pattern may include a data errorpattern that occurs corresponding to the data storage pattern withrespect to the data stored between the adjacent cells of the MLC array110. According to example embodiments, the read error pattern mayinclude the data error pattern that occurs due to the lateral electricfield between the adjacent cells of the MLC array 110. The data errorpattern may correspond to a threshold voltage change of the MLC array110 due to the lateral charge movement caused by the lateral electricfield, and the codeword determination unit 123 may select the codewordincluding the data error pattern.

When a number of bit errors with respect to the analyzed bit error doesnot increase or decrease, the codeword determination unit 123 may selectthe codeword based on the read error pattern.

According to example embodiments, the codeword determination unit 123may analyze frequency information about the read error pattern, and mayselect the codeword having a high or maximum level of association withthe read error pattern.

According to example embodiments, the codeword determination unit 123may analyze a Hamming distance between the read word and each of a setof candidate codewords, and may select the codeword in which theanalyzed Hamming distance is below a reference value or the minimum. TheHamming distance may denote a number of corresponding bit values betweenbinary codes having the same bit number, the bit values being differentfrom each other.

According to example embodiments, the MLC array 110 may record, in aseparate dummy cell, error pattern information about a weight of theread error pattern including data before encoding, and the codeworddetermination unit 123 may select the codeword based on at least one ofthe error pattern information and the analyzed Hamming distance. Thecodeword determination unit 123 may select a codeword in which theweight of the read error pattern is above a reference value or thehighest and the Hamming distance is below a reference value or theminimum.

An example embodiment of FIG. 3 may denote a case where the MLCs in MLCarray 110 store 2-bit data, however, example embodiments may be appliedto a case where the MLCs store m-bit data (m>2).

Hereinafter, referring to FIGS. 4 and 5, an error correction method whena read word is outside an error correcting capability range is describedin detail.

FIG. 4 is a flowchart illustrating a method of correcting a read erroraccording to example embodiments.

Referring to FIG. 4, in operation S410, the method of correcting theread error may include reading and extracting a read word from an MLCarray.

In operation S420, the method may include determining whether the numberof errors in the read word being read and extracted from the MLC array110 exists in an error correcting capability range.

In operation S430, the method may include either increasing ordecreasing a read voltage applied to the MLC array 110 when the numberof errors in the read word is outside the error correcting capabilityrange, analyzing a bit error based on the increase or decrease of theread voltage, and selecting a codeword corresponding to the analyzed biterror based on a selected read error pattern.

Hereinafter, referring to FIGS. 5A through 5C, operation 5430 isdescribed in detail.

FIG. 5A is a flowchart illustrating a method of selecting a codewordbased on a read error pattern to correct an error according to exampleembodiments.

Referring to FIG. 5A, in operation S421, when the number of errors inthe read word is outside the error correcting capability range inoperation 5420, the method may include either increasing or decreasing aread voltage to change the read voltage.

In operation S422, the method may include reading and extracting theread word again. In operation S423, the method may include determiningagain whether the number of errors in the read word being read andextracted again exists in the error correcting capability range.

When the number of errors in the read word being read and extractedagain exists in the error correcting capability range, the method mayproceed to operation S440.

Alternatively, in operation S424, when the number of errors in the readword being read and extracted again is outside the error correctingcapability range, the method may determine whether a read voltageapplied to the MLC array 110 is lower than or equal to a thresholdvoltage. When the read voltage is higher than the threshold voltage, themethod may proceed to operation S421, change the read voltage again, anddetermine whether the number of errors in the read word being read andextracted again exists in the error correcting capability range, andwhether the changed read voltage is lower than or equal to the thresholdvoltage.

Alternatively, when the read voltage is lower than or equal to thethreshold voltage in operation S424, the method may determine whether anumber of bit errors increases or decreases in operation S425, and mayproceed to operation 5426 only when the number of bit errors does notincrease or decrease, which may indicate the number of bit errors isminimum.

When the number of bit errors increases or decreases, the method mayinclude changing the read voltage again and repeating a process fromoperations S421 through S424.

In operation S426, when the number of bit errors does not increase ordecrease, or the number of bit errors is below a reference value or at aminimum in operation S425, the method may include analyzing frequencyinformation about the read error pattern, and selecting the codeword inwhich the frequency information is above a reference value or at amaximum. Since the codeword having a high or maximum level ofassociation with the read error patterns may have a strong possibilityof being the actual codeword compared with other candidate codewords,the method may selects the codeword in which the frequency informationindicates a high or maximum level of association with the read errorpattern.

FIG. 5B is a flowchart illustrating another method of selecting acodeword based on a read error pattern to correct an error according toexample embodiments.

Referring to FIG. 5B, since a process from operations 5421 through S425may be the same as FIG. 5A, descriptions thereof are omitted.

In operation S427, the method of selecting the codeword based on theread error pattern to correct the error according to example embodimentsmay include analyzing a Hamming distance between the read word beingread and extracted again and each of a set of candidate codewords, andselecting the codeword for which the Hamming distance is below areference value or the lowest of the candidate codewords, and level ofassociation of the codeword with the read error pattern is above areference level or the highest of the candidate codewords.

FIG. 5C is a flowchart illustrating still another method of selecting acodeword based on a read error pattern to correct an error according toexample embodiments.

Referring to FIG. 5C, since a process from operations S421 through S425may be the same as FIG. 5A, descriptions thereof are omitted.

In operation S428, the method of selecting the codeword based on theread error pattern to correct the error according to example embodimentsmay include selecting the codeword based on error pattern informationabout a weight of the read error pattern included in a dummy cell of anMLC array, and a Hamming distance analyzed by considering the read wordbeing read and extracted again and the bit error. The method may includeselecting the codeword in which the weight is above a reference level orhighest from among a codeword group including codewords, from among thecandidate codewords, having a Hamming distance that is below a referencevalue or lowest of the candidate codewords. The weight of the read errorpattern may be based on frequency information about the read errorpattern. For example, codewords for which a particular read errorpattern has occurred many times may have a higher weight with respect tothe particular read error pattern than codewords for which theparticular read error pattern has occurred few times or no times.

Referring to FIG. 4 again, in operation S440, when the number of errorsin the read word exists in the error correcting capability range inoperation S420, the method may include decoding the codewordcorresponding to the read word to output the codeword, and decoding thecodeword selected based on the read error pattern in operation S430 tooutput the codeword.

The error correction method according to example embodiments may berecorded in computer-readable media including program instructions toimplement various operations embodied by a computer. The media may alsoinclude, alone or in combination with the program instructions, datafiles, data structures, and the like. The media and program instructionsmay be those specially designed and constructed for the purposes ofexample embodiments, or they may be of the kind well-known and availableto those having skill in the computer software arts. Examples ofcomputer-readable media include magnetic media, for example hard disks,floppy disks, and magnetic tape; optical media, for example CD ROM disksand DVD; magneto-optical media, for example optical disks; and hardwaredevices that are specially configured to store and perform programinstructions, for example read-only memory (ROM), random access memory(RAM), flash memory, and the like. Examples of program instructionsinclude both machine code, for example produced by a compiler, and filescontaining higher level code that may be executed by the computer usingan interpreter. The described hardware devices may be configured to actas one or more software modules in order to perform the operations ofexample embodiments.

Memory devices and/or memory controllers according to exampleembodiments may be embodied using various types of packages. Forexample, the flash memory devices and/or memory controllers may beembodied using packages, for example Package on Packages (PoPs), BallGrid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded ChipCarrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack,Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack (MQFP), Quad Flatpack (QFP),Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System InPackage (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package(WFP), Wafer-Level Processed Stack Package (WSP), and the like.

The flash memory devices and/or the memory controllers may constitutememory cards. In this case, the memory controllers may be constructed tocommunicate with an external device for example, a host using any one ofvarious types of interface protocols, for example a Universal Serial Bus(USB), a Multi Media Card (MMC), a Peripheral ComponentInterconnect-Express (PCI-E), Serial Advanced Technology Attachment(SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI),Enhanced Small Device Interface (ESDI), and Integrated Drive Electronics(IDE).

The flash memory devices may be non-volatile memory devices that canmaintain stored data even when power is cut off. According to anincrease in the use of mobile devices, for example a cellular phone, apersonal digital assistant (PDA), a digital camera, a portable gameconsole, and an MP3 player, the flash memory devices may be more widelyused as data storage and code storage. The flash memory devices may beused in home applications, for example a high definition television(HDTV), a digital video disk (DVD), a router, and a Global PositioningSystem (GPS).

A computing system according to example embodiments may include amicroprocessor that is electrically connected with a bus, a userinterface, a modem, for example a baseband chipset, a memory controller,and a flash memory device. The flash memory device may store N-bit datavia the memory controller. The N-bit data is processed or will beprocessed by the microprocessor and N may be 1 or an integer greaterthan 1. When the computing system is a mobile apparatus, a battery maybe additionally provided to supply operation voltage of the computingsystem.

It will be apparent to those of ordinary skill in the art that thecomputing system according to example embodiments may further include anapplication chipset, a camera image processor (CIS), a mobile DynamicRandom Access Memory (DRAM), and the like. For example, the memorycontroller and the flash memory device may constitute a solid statedrive/disk (SSD) that uses a non-volatile memory to store data.

Example embodiments having thus been described, it will be obvious thatthe same may be varied in many ways. Such variations are not to beregarded as a departure from the intended spirit and scope of exampleembodiments, and all such modifications as would be obvious to oneskilled in the art are intended to be included within the scope of thefollowing claims.

What is claimed is:
 1. An error correction circuit comprising: adetermination unit configured to determine whether a number of errors ina read word being read and extracted from a multi-level cell (MLC) iswithin an error correcting capability range; a read voltage control unitconfigured to either increase or decrease a read voltage applied to theMLC when the number of errors is outside the error correcting capabilityrange; a codeword determination unit configured to analyze a bit errorbased on the increase or decrease of the read voltage, and to select acodeword corresponding to the analyzed bit error based on a selectedread error pattern; and a decoding unit configured to decode a codewordfor the read word when the number of errors is less than or equal to theerror correcting capability range, or to decode the codeword selected bythe codeword determination unit, thereby correcting the errors, whereinthe codeword determination unit is configured such that the codeworddetermination unit analyzes frequency information for the read errorpattern, the frequency information includes information indicating anumber of times the read error pattern has occurred for each of one ormore codewords, and the selected codeword is a codeword for which thenumber of times the read error pattern has occurred exceeds a referencenumber of times.
 2. The circuit of claim 1, wherein, the codeworddetermination unit is configured such that when a number of bit errorswith respect to the analyzed bit error does not increase or decrease,the codeword determination unit selects the codeword based on the readerror pattern.
 3. The circuit of claim 1, wherein the codeworddetermination unit is configured such that the codeword determinationunit analyzes a Hamming distance between the read word and the codeword,and the selected codeword is a codeword having a Hamming distance belowa reference value.
 4. The circuit of claim 3, wherein the MLC storeserror pattern information about a weight of the read error patternincluding data before encoding, and the codeword determination unit isconfigured such that the codeword determination unit selects thecodeword based on at least one of the error pattern information and theanalyzed Hamming distance.
 5. The circuit of claim 1, wherein the readerror pattern includes a data error pattern that occurs corresponding toa data storage pattern between adjacent cells of the MLC.
 6. The circuitof claim 1, wherein the read error pattern is associated with a dataerror pattern that occurs due to a lateral electric field betweenadjacent cells of the MLC.
 7. The circuit of claim 6, wherein the dataerror pattern corresponds to a threshold voltage change of the MLC dueto a lateral charge movement caused by the lateral electric field, andthe codeword determination unit is configured such that the codeworddetermination unit selects the codeword associated with the data errorpattern.
 8. A memory device comprising: an MLC array including aplurality of MLCs; an error correction unit configured to analyze a biterror, when a number of errors in a read word being read and extractedfrom an MLC is outside an error correcting capability range, and toselect and decode a codeword with respect to the read word based on aselected read error pattern; and a host interface configured to transmitthe decoded codeword to a host, wherein the error correction unitincludes, a determination unit configured to determine whether thenumber of errors exists in the error correcting capability range, a readvoltage control unit configured to either increase or decrease a readvoltage applied to the MLC when the number of errors is outside theerror correcting capability range, a codeword determination unitconfigured to analyze the bit error based on the increase or decrease ofthe read voltage, and to select the codeword corresponding to theanalyzed bit error based on the read error pattern, and a decoding unitconfigured to decode a codeword for the read word when the number oferrors is less than or equal to the error correcting capability range,or to decode the codeword selected by the codeword determination unit,thereby correcting the errors, and wherein the codeword determinationunit is configured such that the codeword determination unit analyzesfrequency information for the read error pattern, the frequencyinformation includes information indicating a number of times the readerror pattern has occurred for each of one or more codewords, and theselected codeword is a codeword for which the number of times the readerror pattern has occurred exceeds a reference number of times.
 9. Thememory device of claim 8, wherein the memory device is a Charge TrapFlash (CTF) memory device.
 10. An error correction method comprising:determining whether a number of errors in a word being read andextracted from an MLC is within an error correcting capability range;either increasing or decreasing a read voltage applied to the MLC whenthe number of errors is outside the error correcting capability range;analyzing a bit error based on the increase or decrease of the readvoltage, and selecting a codeword corresponding to the analyzed biterror based on a selected read error pattern; and decoding a codewordfor the read word when the number of errors is less than or equal to theerror correcting capability range, or decoding the codeword selected bythe codeword determination unit, thereby correcting the errors, whereinthe analyzing and selecting includes analyzing frequency informationabout the read error pattern included in the codeword, and the selectedcodeword is a codeword for which a number of times the read errorpattern has occurred exceeds a reference number of times.
 11. The methodof claim 10, wherein the analyzing and selecting analyzes a Hammingdistance to the read word and the bit error, and the selected codewordis a codeword having a Hamming distance below a reference value.
 12. Themethod of claim 11, wherein the MLC stores error pattern informationabout a weight of the read error pattern including data before encoding,and the analyzing and selecting includes selecting the codeword based onat least one of the error pattern information and the analyzed Hammingdistance.
 13. A non-transitory computer-readable recording mediumstoring a program for implementing the method of claim 10.